Standard transistor technology, used for years to make processors and RAM memories by the leading chip manufacturers, is running out of steam. It is destined to leave the floor soon to a new and more advanced transistor technology.
Let’s see what this means and why this will allow us to take another leap forward in terms of performance and scalability.
Lithography and transistor architecture
A transistor has a very basic function: it must turn off and on to allow or block precisely the passage of current.
Lithography determines how many transistors can be engraved in a square millimetre of silicon wafer but does not contribute to any electrical characteristic of the transistor. Its architecture instead is accountable for that.
Keeping the gate “short” allows for greater accuracy in controlling the current, for faster devices (i.e. because the carriers didn’t have to travel as far) and for more transistors per square millimetre in the silicon wafer. The pitch-to-shrink technique has allowed Intel to reach 14 nm ++ in its manufacturing process and TSMC (Taiwan Semiconductor Manufacturing Company) around 16 nm.
However, overly aggressive gate length scaling can lead to performance degradation such as:
- “Off-state” leakage current;
- Velocity saturation/mobility degradation;
- Drain-induced barrier lowering (DIBL), caused by encroachment of the drain depletion region into the channel;
- Impact ionization, in which a charge carrier can be affected by other charge carriers;
- Drain punch through, whereby current flows regardless of gate voltage-a phenomenon that can occur if the drain is at high enough voltage compared to the source and the depletion region around the drain extends to the source;
- Surface scattering;
- Channel length modulation;
- Threshold voltage roll-off.
Short-channel effects occur when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junction. In MOSFETs, channel lengths must be greater than the sum of the drain and source depletion widths to avoid edge effects.
The FinFET transistor technology was proposed in 2011 to overcome the lithography issues of past technologies and push the miniaturization process to shorter gate lengths. FinFETs are tri-gate transistors: the channel that connects the source and drain is brought above the silicon plane, forming a fin that brings numerous advantages over previous construction schemes such as:
- lower supply voltage;
- reduced off-state leakage;
- faster switching speed;
- greater control.
However, the communication channel thus designed brings new problems such as the minimum space requirement between the fins for each lithographic process. Minimizing the gate size reduces the fins’ space, especially when the lithographic process is taken to the extreme. As contact pitch continues to shrink, there isn’t enough room to fit two or more fins in a standard cell. That is where the Nanosheet technology comes in.
The new gate-all-around transistors (GAAFET) or Nanosheet technology
The need to push the process to the edge caused engineers to explore other transistor technologies often discarded in the past due to their increased complexity. In GAAFETs, the gate is positioned below the channel, not only in the upper and lateral parts, and “Nanoconnections” are used between the source and drain. The ultimate goal is to stack the ends of the transistor vertically rather than just sideways – hence the term Nanosheet for the similarity with the pages of a book.
GAAFETs were first proposed in 1990, well before FinFETs, but FinFETs turned out to be easier to implement in production. In the case of GAAFETs, the transistors will use alternating layers of silicon and SiGe (Silicon Germanium) together with a special “spacer” that defines the width of the gate.
The advantage of GAAFETs is that the gate size can be significantly reduced compared to the 15 nm achieved in finFET transistors. According to the first assessments of the experts, although the companies have not yet shared technical data, the gate could shrink below 7 nm.
The transistor architecture and construction processes are not the only aspects that the experts are focusing on these days. Other alternative technologies are currently being developed. Everyone agrees that vertical layer stacking is the way to go that will make completely obsolete today’s transistors, enabling much higher performance for future processors and memories.
A topic that deserves special attention is the development of 3D Integrated circuits composed of multiple chips not placed on the same level, but stacked, something that goes beyond the conventional schemes based on the simple use of a monolithic chip.
Instead of having a large monolithic chip that develops horizontally, several smaller chips are arranged vertically and interconnected among them. SoIC (System on Integrated Chips) looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded.
Increasing the number of connections reduces the need for higher clock speed, with therefore much lower power consumption for each bit of information transmitted (doubling the clock speed of a chip quadruples its consumption). In addition, the SoIC technology allows for higher computing efficiency, wilder data bandwidth, higher functionality packaging density and lower communication latency. However, 3D packaging is challenging and requires overcoming three major challenges – thermal, power delivery, and production yield.
The secret is all here: transform a monolithic SoC into a 3DIC that uses SoIC interconnections, opening a new frontier in terms of improving performance and reducing energy consumption. So far, this technology has been used to manufacture memories such as HBM and 3D NANDs. The next step is to merge logic and memory in a 3DIC configuration or to combine different pieces of logic and produce CPU and GPU with more conventional form factors and sockets.